Within the data processing industry, there has been continuing effort directed to increasing the performance of a computer system while at the same time decreasing the cost of the system. Among the many variables to be considered in an attempt to increase the performance of the data processing system, two very important considerations are the data transfer rate between processors employed within the system and the system memory modules, and the flexibility of the processors to interface with different types of memory modules.
In many prior art memory modules, the transfer of data between the module and a processor is limited to a single data word in response to a single memory request. Since there is an inherent cost in increasing the size of a data word, there are practical upper limits with regard to the number of bits that can be included in a data word and transferred in parallel by the memory module.
A second type of prior art memory module maintains the limitation of only transferring one data word in parallel but provides the capability for transferring two data words by means of successive bus cycles issued in response to a single memory request. This increases the efficiency of the entire data processing system because much of the overhead in obtaining a second data word is avoided since it is automatically transmitted in a second second-half bus cycle.
With the recent use of integrated circuits as the building blocks of complete computer systems, the physical size of a system has been greatly reduced and, therefore, the lengths of the busses and cables interconnecting the system elements have been significantly shortened. From this has arisen the ability to increase the number of bits of information transferred in parallel along the busses and cables without increasing the overall cost. Thus, in some more recent computer systems it is possible for the memory module to transfer two data words in parallel between the module and the system processors.
A dilemma arises, however, when these different types of memory modules are included within a single computer system. To maximize the efficiency of the system, it is necessary to be able to store information with equal facility in any of the memory modules. However, since the memory modules are capable of different width transfers and different transfer modes, a problem arises when a processor request information stored somewhere in the system's memory without knowing the type of module that will be responding to the memory request. It is most unsatisfactory to limit the central processors to information transfer constraints dictated by the least efficient memory module, but at the same time the processors must be assured that a memory request will be satisfied in its entirety.